View source for CMV12000 Register Blocks

== Sensor Pipeline ==

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{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Description
|-
| 0x600xxxxx || CMV SPI register mapping
|-
| 0x601xxxxx || Capture Control/Address Gen.
|-
| 0x602xxxxx || LVDS input delay registers
|-
| 0x603xxxxx || RCN noise correction LUTs
|-
| 0x604xxxxx || CMV/AXI PLL dynalic reconf (disabled)
|-
| 0x605xxxxx ||  Linearization LUTs
|}



{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Description
|+ Display Pipeline
|-
| 0x800xxxxx || Display Scan Generator 
|-
| 0x801xxxxx || Display Control/Address Gen.
|-
| 0x802xxxxx || Component Matrix 4x4
|-
| 0x803xxxxx || Gamma Correction LUTs
|-
| 0x804xxxxx || HDMI PLL dynamic reconf
|-
| 0x805xxxxx || Illumination Control (testing)
|}


	
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Description
|+ 0x600xxxxx CMV SPI Register Mapping
|-
| 0x60000000 || RW || [15:0] || CMV Register 0
|-
| 0x60000004 || RW || [15:0] || CMV Register 1
|-
| ..........  ||  || ...... || ..............
|- 
| 0x600001F8 || RW || [15:0] || CMV Register 126
|-
| 0x600001FC || RO || [15:0] || CMV Register 127
|}
  	
  	

{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x601xxxxx     Capture Control/Address Gen. (Read Only Data)
|-
| <b>0x60100000</b> || RO || [31:8]  || 0x524547 || Identifier "REG"
|-
| 0x60100000 || RO || [7:4] || 0x0 || Revision 0
|-
| <b>0x60100000</b> || RO || [3:0] || 0x8 || Split x0100
|-
| 0x60100004 || RO || [31:0] || || User Access
|-
| 0x60100008 || RO || [31:0] || || LVDS Match (ch 0-31)
|- 
| 0x6010000C || RO || [31:0] || || LVDS Mismatch (ch 0-31)
|-
| 0x60100010 || RO || [31:0] || || Current Writer Address
|- 
| 0x60100014 || RO || [31:30] || || Write Buffer Selection
|-
| <b>0x60100014</b> || RO || [29:28] || 0x0 || Zero Padding
|-
| 0x60100014 || RO || [27:24] || || Writer Inactive (0-3)
|-
| <b>0x60100014</b> || RO || [23:22] || 0x0 || Zero Padding
|-
| 0x60100014 || RO || [21] || || Fifo Write Error
|-
| <b>0x60100014</b> || RO || [20] || || Fifo Read Error
|-
| 0x60100014 || RO || [19] || || Fifo Full
|-
| <b>0x60100014</b> || RO || [18] || || Fifo High
|-
| 0x60100014 || RO || [17] || || Fifo Low
|-
| <b>0x60100014</b> || RO || [16] || || Fifo Empty
|-
| 0x60100014 || RO || [15:13] || 0x0 || Zero Padding
|-
| <b>0x60100014</b> || RO || [12] || || Button Down State
|-
| 0x60100014 || RO || [11] || || Button Up State
|-
| <b>0x60100014</b> || RO || [10] || || Button Right State
|-
| 0x60100014 || RO || [9] || ||  Button Left State
|-
| <b>0x60100014</b> || RO || [8] || || Button Center State
|-
| 0x60100014 || RO || [7:0] || || Switch State (0-7)
|- 
| <b>0x60100014</b> || RO || [31] || || Capture Sequence Drone
|-
| 0x60100014 || RO || [30:28] || || Zero Padding
|-
| <b>0x60100014</b> || RO || [27:16] || || CSeq Frame Count
|-
| 0x60100014|| RO || [15:0] || || Zero Padding
|}

{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x601xxxxx	Capture Control/Address Gen. (Read/Write Data)
|-  			
| 0x60100100
0x60100104
|| RW
RW
|| [31:0]
[31:0]
|| 0x18000000
0x19FF0000
|| Write Buffer 0 Base
Write Buffer 0 End Pattern
|-
| 0x60100108
0x6010010C
|| RW
RW
|| [31:0]
[31:0]
|| 0x1A000000
0x1BFF0000
|| Write Buffer 1 Base	
Write Buffer 1 End Pattern
|-
| 0x60100110
0x60100114
|| RW
RW
|| [31:0]
[31:0]
|| 0x1C000000
0x1DFF0000
|| Write Buffer 2 Base
Write Buffer 2 End Pattern
|- 
|0x60100118
0x6010011C
|| RW
RW
|| [31:0]
[31:0]
|| 0x1E000000
0x1FFF0000
|| Write Buffer 3 Base
Write Buffer 3 End Pattern
|-
|| 0x60100120 || RW || [31:0] || 0x00000080 || Column Increment
|-
| 0x60100124 || RW || [31:0] || 0x00000080 || Row Increment
|-
| 0x60100128 || RW || [11:0] || 0x0000007E || Column Burst Count  
|- 
| 0x6010012C 
|| RW 
RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW 
<br> RW
<br> RW 
| [31:24]
[21]
<br> [20]
<br> [19:16]
<br> [15:12]
<br> [8] 
<br> [7] 
<br> [6] 
<br> [5] 
<br> [4] 
<br> [0] 
| 0xFC	
0x1
<br> 0x1
<br> 0xF
<br> 0xF
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
|Write Address Strobe
RCN Clip Overflow
<br> RCN Clip Underflow
<br> Writer Enable
<br> Buffer Enable
<br> SerDes Reset
<br> Buffer Switch Request
<br> Buffer Load Request
<br> Buffer Reset Request
<br> Buffer Block Request
<br> Fifo Reset
|-
| 0x60100130 || RW || [11:0] || 0xA95 || LVDS Training Pattern
|- 
| 0x60100134 || RW
RW
<br>  RW
|| [18:16] 
[10:8] 
<br> [2:0] 	
|| 0x07
0x07
<br> 0x07
|| Active Data Mask
Capture Data Mask
<br> Capture Data Value
|-
| 0x60100138
|| RW
RW 
<br> RW
|| [23:16]	
[8]	
<br> [7:0]	
|| 0x00	
0x0
<br> 0x00
|| LED Override Mask (0-7)
Done LED Value
<br> LED Override Value (0-7)
|-
| 0x6010013C
|| RW
RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
|| [28] 
[27] 
<br>[26] 
<br> [25] 
<br> [24] 
<br> [23:16] 
<br> [12] 
<br> [11] 
<br> [10] 
<br> [9] 
<br> [8] 	
<br> [7:0] 
|| 0x0
0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x00
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x00
|| Button Down Override Enable
Button Up Override Enable
<br> Button Right Override Enable
<br> Button Left Override Enable
<br> Button Center Override Enable
<br> Switch Override Enable (0-7)
<br> Button Down Override
<br> Button Up Override
<br> Button Right Override
<br> Button Left Override
<br> Button Center Override
<br> Switch Override (0-7)
|}