View source for USB 3.0 Plugin Module Gearwork

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== Project Summary ==

The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gbit/s or more. Several high speed plugin modules like HDMI, DP or SDI can be plugged into these thereby providing additional functionalities.Currently, the AXIOM Beta lacks a USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. This project is about implementing a USB 3.0 gearwork using the LVDS connection exposed by the PCIe connectors for streaming 4K 12-bit video at 25 FPS. There is no aftermarket solutions for high speed LVDS to USB 3.0 conversion. Only 16/24/32-bit parallel data to USB 3.0 bridges are available. Hence, a USB 3.0 plugin module has been designed by apertus° featuring a MachXO2 Lattice FPGA and FT601Q/FT602 FTDI IC for this purpose.

'''Google Summer of Code 2019 project.'''

'''Mentored by: Bertl.'''

'''Implemented by: Apurva Nandan'''

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== Important URLs ==

* [https://github.com/apurvanandan1997/usb_plug_mod_ber GSoC 2019 Code]

* [https://github.com/apurvanandan1997/SerDes_T871_A/blob/master/Proposal/Apertus_USB_3.0_GearWork_Project_Proposal.pdf Proposal]

* [https://github.com/apurvanandan1997/usb_plug_mod_ber/Report.pdf Report]

* [https://summerofcode.withgoogle.com/projects/#4870344697970688 Project Page at GSoC'19 ]

* [https://lab.apertus.org/T885 Lab Task ]

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== References ==

* [https://wiki.apertus.org/index.php/1x_USB_3.0_Plugin_Module USB 3.0 Plugin Module Wiki ]

* [https://www.latticesemi.com/Products/FPGAandCPLD/MachXO2 Lattice MachXO2 FPGA]

*  [https://www.latticesemi.com/view_document?document_id=39084 Implementing High-Speed Interfaces with MachXO2 Devices - TN1203]

* [https://www.ftdichip.com/Products/ICs/FT600.html FTDI FT601Q chip]