Difference between revisions of "USB 3.0 Plugin Module Gearwork"
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== Project Summary == | == Project Summary == | ||
The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gbit/s or more. Several high speed plugin modules like HDMI, DP or SDI can be plugged into these thereby providing additional functionalities. The AXIOM Beta lacked a USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. In this project I wrote all the HDL code for gearwork of the USB 3.0 plugin module designed by apertus° so that it can transfer the live 4K video data at 20+ FPS | The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gbit/s or more. Several high speed plugin modules like HDMI, DP or SDI can be plugged into these thereby providing additional functionalities. The AXIOM Beta lacked a USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. In this project I wrote all the HDL code for gearwork of the USB 3.0 plugin module designed by apertus° so that it can transfer the live 4K video data at 20+ FPS from the LVDS lanes exposed by the PCIe connectors to the connected PC by use of a USB 3.0 port. | ||
'''Google Summer of Code 2019 project.''' | '''Google Summer of Code 2019 project.''' | ||
Revision as of 17:52, 23 August 2019
1 Project Summary
The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gbit/s or more. Several high speed plugin modules like HDMI, DP or SDI can be plugged into these thereby providing additional functionalities. The AXIOM Beta lacked a USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. In this project I wrote all the HDL code for gearwork of the USB 3.0 plugin module designed by apertus° so that it can transfer the live 4K video data at 20+ FPS from the LVDS lanes exposed by the PCIe connectors to the connected PC by use of a USB 3.0 port.
Google Summer of Code 2019 project.
Mentored by: Bertl
Implemented by: Apurva Nandan