Difference between revisions of "Beta Interface Dummy Board"
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[[File: | [[File:00-DIB-001- AXIOM Beta Dummy Interface Board V0.13R1.1 Top Populated Show 1150Web.jpg | 1150px |]] | ||
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[https://wiki.apertus.org/images/8/84/00-DIB-001-_AXIOM_Beta_Dummy_Interface_Board_V0.13R1.1_Top_Populated_Show_3000.jpg Full size image.] | |||
The AXIOM Beta Dummy Interface Board acts as a bridge between the Image Sensor Board and the rest of the camera. It connects the LVDS pairs from the Main Board with the Image Sensor Board. Capacitors to smooth-out power ripples and provide buffering have also been incorporated. It should be noted that this printed circuit board is extremely specific to the CMV12000 image sensor. | |||
[[File:ABCS-DIB-02a- AXIOM Beta Dummy Interface Board V0.13R1.1 Top Populated 1150web.jpg | 1150px |]] | |||
[https://wiki.apertus.org/images/7/7e/ABCS-DIB-02a-_AXIOM_Beta_Dummy_Interface_Board_V0.13R1.1_Top_Populated_3000.jpg Full size image.] | |||
'''Note:''' The present iteration of Interface Board limits image sensor throughput to 150FPS@4K. This current Beta Interface Dummy Board connects 32+3 of the 64+3 [https://en.wikipedia.org/wiki/Low-voltage_differential_signaling LVDS] channels available in the CMV12000. A 'Smart Sensor Interface Board', however, would allow the camera to get 4K@300 FPS into the pipeline. High speed memory on this board would allow buffering of images for high speed recording bursts or temporal binning/averaging and thus allow for use of the microzed with output being slower than acquisition bandwidths. Requires 400+ IO so XC7A200T FBG676 FPGA which is 200+€ is the only option (covered by webpack license though). Herbert has done a few tests to see if it would be possible to do with OSHpark stackups and the conclusion was: doable but non-trivial. The general design is rather straight forward (connect 36 LVDS pairs on one end and 80 LVDS pairs on the other end to an FPGA). But it is also completely unknown how much processing can be done there and what that means for cooling, etc (not only the MicroZed, but the Beta Interface Board itself will also heat up). The simplest application is the 'gearwork' between SB and MB. It could also run a sensor emulation eliminating the SFE for many development task and/or testing. It could do fancy stuff with the sensor data (preprocessing). | |||
If you'd like to assist with development in this area please make [https://www.apertus.org/contact contact]. | |||
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=Revisions= | =Revisions= | ||
'''Current:''' | |||
[[axiom beta interface dummy v0.13]] | [[axiom beta interface dummy v0.13]] | ||
Sources: https://apertus-open-source-cinema.github.io/pcbs/index.html#/boards/AXIOM%20Beta%20Interface%20Dummy/0.13%20r1.6/default/Beta | |||
'''Archive:''' | |||
[[axiom beta interface dummy v0.9]] | [[axiom beta interface dummy v0.9]] | ||
Latest revision as of 16:06, 18 December 2021
The AXIOM Beta Dummy Interface Board acts as a bridge between the Image Sensor Board and the rest of the camera. It connects the LVDS pairs from the Main Board with the Image Sensor Board. Capacitors to smooth-out power ripples and provide buffering have also been incorporated. It should be noted that this printed circuit board is extremely specific to the CMV12000 image sensor.
Note: The present iteration of Interface Board limits image sensor throughput to 150FPS@4K. This current Beta Interface Dummy Board connects 32+3 of the 64+3 LVDS channels available in the CMV12000. A 'Smart Sensor Interface Board', however, would allow the camera to get 4K@300 FPS into the pipeline. High speed memory on this board would allow buffering of images for high speed recording bursts or temporal binning/averaging and thus allow for use of the microzed with output being slower than acquisition bandwidths. Requires 400+ IO so XC7A200T FBG676 FPGA which is 200+€ is the only option (covered by webpack license though). Herbert has done a few tests to see if it would be possible to do with OSHpark stackups and the conclusion was: doable but non-trivial. The general design is rather straight forward (connect 36 LVDS pairs on one end and 80 LVDS pairs on the other end to an FPGA). But it is also completely unknown how much processing can be done there and what that means for cooling, etc (not only the MicroZed, but the Beta Interface Board itself will also heat up). The simplest application is the 'gearwork' between SB and MB. It could also run a sensor emulation eliminating the SFE for many development task and/or testing. It could do fancy stuff with the sensor data (preprocessing).
If you'd like to assist with development in this area please make contact.
PCB Top.
PCB Bottom.
Revisions
Current:
axiom beta interface dummy v0.13
Archive:
axiom beta interface dummy v0.9