Difference between revisions of "CMV12000 Register Blocks"

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= CMV12000 Register Blocks =
[[Image_Sensors | Image Sensors main page]]
== Sensor Pipeline ==


<css>
  th.reg { width:4em; border:0px ! important ; color:#000; }


  tr:nth-child(2n+1)
== Sensor Pipeline ==
    {
    background:#cef
      }
 
  td.odd { color:#F00 }
  td.even { color:#000 }
 
</css>
   
   
{| class="wikitable" style="text-align:center"
{| class="wikitable" style="text-align:center"
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| 0x605xxxxx ||  Linearization LUTs
| 0x605xxxxx ||  Linearization LUTs
|}
|}




Line 35: Line 25:
{| class="wikitable" style="text-align:center"
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Description
!class="reg"| Address || class="reg"| Description
|+ Display Pipeline
|+ Display Pipeline
|-
|-
| 0x800xxxxx || Display Scan Generator  
| 0x800xxxxx || Display Scan Generator  
Line 49: Line 41:
| 0x805xxxxx || Illumination Control (testing)
| 0x805xxxxx || Illumination Control (testing)
|}
|}




Line 54: Line 47:
{| class="wikitable" style="text-align:center"
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Description
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Description
|+ 0x600xxxxx     CMV SPI Register Mapping
|+ 0x600xxxxx CMV SPI Register Mapping
|-
|-
| 0x60000000 || RW || [15:0] || CMV Register 0
| 0x60000000 || RW || [15:0] || CMV Register 0
Line 68: Line 61:
  
  
  
  


{| class="wikitable" style="text-align:center"
{| class="wikitable" style="text-align:center"
Line 73: Line 67:
|+ 0x601xxxxx    Capture Control/Address Gen. (Read Only Data)
|+ 0x601xxxxx    Capture Control/Address Gen. (Read Only Data)
|-
|-
| 0x60100000 || RO <br> RO <br> RO || [31:8]  <br> [7:4] <br>[3:0] || 0x524547 <br> 0x0 <br> 0x8 || Identifier "REG" <br> Revision 0 <br> Split x0100
| 0x60100000 || RO || [31:8]  || 0x524547 || Identifier "REG"
|-
| 0x60100000 || RO || [7:4] || 0x0 || Revision 0
|-
| 0x60100000 || RO || [3:0] || 0x8 || Split x0100
|-
|. ||. ||. ||. ||.
|-
|-
| 0x60100004 || RO || [31:0] || || User Access
| 0x60100004 || RO || [31:0] || || User Access
|-
|. ||. ||. ||. ||.
|-
|-
| 0x60100008 || RO || [31:0] || || LVDS Match (ch 0-31)
| 0x60100008 || RO || [31:0] || || LVDS Match (ch 0-31)
|-
|. ||. ||. ||. ||.
|-  
|-  
| 0x6010000C || RO || [31:0] || || LVDS Mismatch (ch 0-31)
| 0x6010000C || RO || [31:0] || || LVDS Mismatch (ch 0-31)
|-
|. ||. ||. ||. ||.
|-
|-
| 0x60100010 || RO || [31:0] || || Current Writer Address
| 0x60100010 || RO || [31:0] || || Current Writer Address
|-
|. ||. ||. ||. ||.
|-  
|-  
| 0x60100014 ||
| 0x60100014 || RO || [31:30] || || Write Buffer Selection
RO
|-
<br> RO
| 0x60100014 || RO || [29:28] || 0x0 || Zero Padding
<br> RO
|-
<br> RO
| 0x60100014 || RO || [27:24] || || Writer Inactive (0-3)
<br> RO
|-
<br> RO
| 0x60100014 || RO || [23:22] || 0x0 || Zero Padding
<br> RO
|-
<br> RO
| 0x60100014 || RO || [21] || || Fifo Write Error
<br> RO
|-
<br> RO
| 0x60100014 || RO || [20] || || Fifo Read Error
<br> RO
|-
<br> RO
| 0x60100014 || RO || [19] || || Fifo Full
<br> RO
|-
<br> RO
| 0x60100014 || RO || [18] || || Fifo High
<br> RO
|-
<br> RO
| 0x60100014 || RO || [17] || || Fifo Low
<br> RO
|-
|| [31:30]
| 0x60100014 || RO || [16] || || Fifo Empty
[29:28]
|-
<br> [27:24]
| 0x60100014 || RO || [15:13] || 0x0 || Zero Padding
<br> [23:22]
|-
<br> [21]
| 0x60100014 || RO || [12] || || Button Down State
<br> [20]
|-
<br> [19]
| 0x60100014 || RO || [11] || || Button Up State
<br> [18]
|-
<br> [17]
| 0x60100014 || RO || [10] || || Button Right State
<br> [16]
|-
<br> [15:13]
| 0x60100014 || RO || [9] || ||  Button Left State
<br> [12]
|-
<br> [11]
| 0x60100014 || RO || [8] || || Button Center State
<br> [10]
|-
<br> [9]
| 0x60100014 || RO || [7:0] || || Switch State (0-7)
<br> [8]
|-
<br> [7:0]
|. ||. ||. ||. ||.
|| 0x0
<br>
<br> 0x0
<br>
<br>
<br>
<br>
<br>
<br>
<br> 0x0
<br>
<br>
<br>
<br>
<br>
<br>
<br>
|| Write Buffer Selection
Zero Padding
<br> Writer Inactive (0-3)
<br> Zero Padding
<br> Fifo Write Error
<br> Fifo Read Error
<br> Fifo Full
<br> Fifo High
<br> Fifo Low
<br> Fifo Empty
<br> Zero Padding
<br> Button Down State
<br> Button Up State
<br> Button Right State
<br> Button Left State
<br> Button Center State
<br> Switch State (0-7)
|-  
|-  
| 0x60100018 || RO <br> RO<br> RO <br> RO ||[31] <br> [30:28] <br> [27:16] <br> [15:0] || || Capture Sequencer Done <br> Zero Padding <br> CSeq Frame Count <br> Zero Padding
| 0x60100018 || RO || [31] || || Capture Sequence Drone
|-
| 0x60100018 || RO || [30:28] || || Zero Padding
|-
| 0x60100018 || RO || [27:16] || || CSeq Frame Count
|-
| 0x60100018|| RO || [15:0] || || Zero Padding
|}
|}
 
 
 




{| class="wikitable" style="text-align:center"
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Description
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x601xxxxx Capture Control/Address Gen. (Read/Write Data)
|+ 0x601xxxxx Capture Control/Address Gen. (Read/Write Data)
|- 
|- 
| 0x60100100
| 0x60100100 || RW || [31:0] || 0x18000000 || Write Buffer 0 Base
0x60100104
|-
|| RW
| 0x60100104 || RW || [31:0] || 0x19FF0000 || Write Buffer 0 End Pattern
RW
|-
|| [31:0]
|. ||. ||. ||. ||.
[31:0]
|-
|| 0x18000000
| 0x60100108 || RW || [31:0] || 0x1A000000 || Write Buffer 1 Base
0x19FF0000
|-
|| Write Buffer 0 Base
| 0x6010010C || RW || [31:0] || 0x1BFF0000 || Write Buffer 1 End Pattern
Write Buffer 0 End Pattern
|-
|. ||. ||. ||. ||.
|-
| 0x60100110 || RW || [31:0] || 0x1C000000 || Write Buffer 2 Base
|-
|-
| 0x60100108
| 0x60100114 || RW || [31:0] || 0x1DFF0000 || Write Buffer 2 End Pattern
0x6010010C
|| RW
RW
|| [31:0]
[31:0]
|| 0x1A000000
0x1BFF0000
|| Write Buffer 1 Base
Write Buffer 1 End Pattern
|-
|-
| 0x60100110
|. ||. ||. ||. ||.
0x60100114
|| RW
RW
|| [31:0]
[31:0]
|| 0x1C000000
0x1DFF0000
|| Write Buffer 2 Base
Write Buffer 2 End Pattern
|-  
|-  
|0x60100118
| 0x60100118 || RW || [31:0] || 0x1E000000 || Write Buffer 3 Base
0x6010011C
|| RW
RW
|| [31:0]
[31:0]
|| 0x1E000000
0x1FFF0000
|| Write Buffer 3 Base
Write Buffer 3 End Pattern
|-
|-
|| 0x60100120 || RW || [31:0] || 0x00000080 || Column Increment
| 0x6010011C || RW || [31:0] || 0x1FFF0000 || Write Buffer 3 End Pattern
|-
|. ||. ||. ||. ||.
|-
| 0x60100120 || RW || [31:0] || 0x00000080 || Column Increment
|-
|. ||. ||. ||. ||.
|-
|-
| 0x60100124 || RW || [31:0] || 0x00000080 || Row Increment
| 0x60100124 || RW || [31:0] || 0x00000080 || Row Increment
|-
|-
| 0x60100128 || RW || [11:0] || 0x0000007E || Column Burst Count
|. ||. ||. ||. ||.
|-
| 0x60100128 || RW || [11:0] || 0x0000007E || Column Burst Count  
|-
|. ||. ||. ||. ||.
|-
| 0x6010012C || RW || [31:24] || 0xFC ||Write Address Strobe
|-
| 0x6010012C || RW || [21] || 0x1 || RCN Clip Overflow
|-
| 0x6010012C || RW || [20] || 0x1 || RCN Clip Underflow
|-  
|-  
| 0x6010012C  
| 0x6010012C || RW || [19:16] || 0xF || Writer Enable
|| RW  
|-
RW
| 0x6010012C || RW || [15:12] || 0xF || Buffer Enable
<br> RW
|-
<br> RW
| 0x6010012C || RW || [8] || 0x0 || SerDes Reset
<br> RW
|-
<br> RW
| 0x6010012C || RW || [7] || 0x0 || Buffer Switch Request
<br> RW
|-
<br> RW
| 0x6010012C || RW || [6] || 0x0 || Buffer Load Request
<br> RW  
|-
<br> RW
| 0x6010012C || RW || [5] || 0x0 || Buffer Reset Request
<br> RW  
|-
| [31:24]
| 0x6010012C || RW || [4] || 0x0 || Buffer Block Request
[21]
|-
<br> [20]
| 0x6010012C || RW || [0] || 0x0 || Fifo Reset
<br> [19:16]
|-
<br> [15:12]
|. ||. ||. ||. ||.
<br> [8]  
|-
<br> [7]  
| 0x60100130 || RW || [11:0] || 0xA95 || LVDS Training Pattern
<br> [6]  
|-
<br> [5]  
|. ||. ||. ||. ||.
<br> [4]  
|-
<br> [0]  
| 0x60100134 || RW || [18:16] || 0x07 || Active Data Mask
| 0xFC
|-
0x1
| 0x60100134 || RW || [10:8] || 0x07 || Capture Data Mask
<br> 0x1
|-
<br> 0xF
| 0x60100134 || RW || [2:0] || 0x07 || Capture Data Value
<br> 0xF
|-
<br> 0x0
|. ||. ||. ||. ||.
<br> 0x0
|-
<br> 0x0
| 0x60100138 || RW || [23:16] || 0x00 || LED Override Mask (0-7)
<br> 0x0
|-
<br> 0x0
| 0x60100138 || RW || [8] || 0x0 || Done LED Value
<br> 0x0
|-
|Write Address Strobe
| 0x60100138 || RW || [7] || 0x00 || LED Override Value (0-7)
RCN Clip Overflow
|-
<br> RCN Clip Underflow
|. ||. ||. ||. ||.
<br> Writer Enable
|-
<br> Buffer Enable
| 0x6010013C || RW || [28] || 0x0 || Button Down Override Enable
<br> SerDes Reset
|-
<br> Buffer Switch Request
| 0x6010013C || RW || [27] || 0x0 || Button Up Override Enable
<br> Buffer Load Request
|-
<br> Buffer Reset Request
| 0x6010013C || RW || [26] || 0x0 || Button Right Override Enable
<br> Buffer Block Request
|-
<br> Fifo Reset
| 0x6010013C || RW || [25] || 0x0 || Button Left Override Enable
|-
| 0x6010013C || RW || [24] || 0x0 || Button Center Override Enable
|-
| 0x6010013C || RW || [23:16] || 0x00 || Switch Override Enable (0-7)
|-
| 0x6010013C || RW || [12] || 0x0 || Button Down Override
|-
| 0x6010013C || RW || [11] || 0x0 || Button Up Override
|-
| 0x6010013C || RW || [10] || 0x0 || Button Right Override
|-
| 0x6010013C || RW || [9] || 0x0 || Button Left Override
|-
| 0x6010013C || RW || [8] || 0x0 || Button Center Override
|-
| 0x6010013C || RW || [7] || 0x00 || Switch Override (0-7)
|}
 
 
 
 
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x602xxxxx LVDS Input Delay
|-
| 0x60200000 || WO || [31] || 0x0 || Bitslip Channel 0
|-
| 0x60200000 || RO || [29] || || Pattern Match Channel 0
|-
| 0x60200000 || RO || [28] || || Pattern Mismatch Channel 0
|-
| 0x60200000 || RW || [4:0] || 0x0  || Delay Value Channel 0
|-
|. ||. ||. ||. ||.
|-
| 0x60200004 || || || || Same for Channel 1
|-
| .......... || || || || ..............
|-
| 0x6020007C || || || || Same for Channel 31
|-
| 0x60200080 || || || || Same for Control Channel
|-
|. ||. ||. ||. ||.
|-
| 0x60200084 || WO || [31] || 0x0 || Word Slip/Phase for all Channels
|-
| 0x60200084 || RW || [4:0] || 0x0 || Delay Value for LVDS Clock
|}
 
 
 
 
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x6030xxxx Column Offset LUTs
|-
| 0x60300000 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 0)
|-
|. ||. ||. ||. ||.
|-
| 0x60300004 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 2)
|-
| 0x60300008 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 4)
|-
| .......... || || || || ..............
|-
| 0x60301FF8 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 4092)
|-
| 0x60301FFC || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 4094)
|-
|. ||. ||. ||. ||.
|-
| 0x60302000 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 1)
|-
|. ||. ||. ||. ||.
|-
| 0x60302004 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 3)
|-
| 0x60302008 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 5)
|-
| .......... || || || || ..............
|-
| 0x60303FF8 || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 4093)
|-
| 0x60303FFC || RW || [11:0] || 0x000 || Signed 12bit Offset (Column 4095)
|}
 
 
 
 
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x6030xxxx Row Offset LUTs
|-
|0x60304000 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 0)
|-
|. ||. ||. ||. ||.
|-
| 0x60304004 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 2)
|-
| 0x60304008 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 4)
|-
| .......... || || || || ..............
|-
| 0x60305FF8 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 4092)
|-
| 0x60305FFC || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 4094)
|-
|. ||. ||. ||. ||.
|-
| 0x60306000 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 1)
|-
|. ||. ||. ||. ||.
|-
| 0x60306004 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 3)
|-
| 0x60306008 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 5)
|-
| .......... || || || || ..............
|-
|-
| 0x60100130
| 0x60307FF8 || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 4093)
| RW  
| [11:0]
| 0xA95
| LVDS Training Pattern
|- style="background-color: #C0C0C0"
| 0x60100134
| RW
RW
<br>  RW
| [18:16]
[10:8]
<br> [2:0]
| 0x07
0x07
<br> 0x07
| Active Data Mask
Capture Data Mask
<br> Capture Data Value
|-
|-
| 0x60100138
| 0x60307FFC || RW || [11:0] || 0x000 || Signed 12bit Offset (Row 4095)
| RW
RW
<br> RW
| [23:16]
[8]
<br> [7:0]
| 0x00
0x0
<br> 0x00
| LED Override Mask (0-7)
Done LED Value
<br> LED Override Value (0-7)
|- style="background-color: #C0C0C0"
| 0x6010013C
| RW
RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
<br> RW
| [28]
[27]
<br>[26]
<br> [25]
<br> [24]
<br> [23:16]
<br> [12]
<br> [11]
<br> [10]
<br> [9]
<br> [8]
<br> [7:0]
| 0x0
0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x00
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x0
<br> 0x00
| Button Down Override Enable
Button Up Override Enable
<br> Button Right Override Enable
<br> Button Left Override Enable
<br> Button Center Override Enable
<br> Switch Override Enable (0-7)
<br> Button Down Override
<br> Button Up Override
<br> Button Right Override
<br> Button Left Override
<br> Button Center Override
<br> Switch Override (0-7)
|}
|}
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x6050xxxx Linearization LUTs
|-
|0x60500000 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 0, Val 0)
|-
|. ||. ||. ||. ||.
|-
| 0x60500004 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 0, Val 1)
|-
| .......... || || || || ..............
|-
| 0x60503FFC || RW || [17:0] || 0x0000 || Signed 18bit (Chan 0, Val 4095)
|-
|. ||. ||. ||. ||.
|-
|0x60504000 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 1, Val 0)
|-
|. ||. ||. ||. ||.
|-
| 0x60504004 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 1, Val 1)
|-
| .......... || || || || ..............
|-
| 0x60507FFC || RW || [17:0] || 0x0000 || Signed 18bit (Chan 1, Val 4095)
|-
|. ||. ||. ||. ||.
|-
| 0x60508000 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 2, Val 0)
|-
|. ||. ||. ||. ||.
|-
| 0x60508004 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 2, Val 1)
|-
| .......... || || || || ..............
|-
| 0x6050BFFC || RW || [17:0] || 0x0000 || Signed 18bit (Chan 2, Val 4095)
|-
|. ||. ||. ||. ||.
|-
| 0x6050C000 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 3, Val 0)
|-
|. ||. ||. ||. ||.
|-
| 0x6050C004 || RW || [17:0] || 0x0000 || Signed 18bit (Chan 3, Val 1)
|-
| .......... || || || || ..............
|-
| 0x6050FFFC || RW || [17:0] || 0x0000 || Signed 18bit (Chan 3, Val 4095)
|}
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x800xxxxx Scan Generator  (Read Only Data)
|-
| 0x80000000 || RO || [31:8] || 0x53434E || Identifier "SCN"
|-
| 0x80000000 || RO || [7:4] || 0x0 || Revision 0
|-
| 0x80000000 || RO || [3:0] || 0x8 || Split x0100
|-
|. ||. ||. ||. ||.
|-
| 0x80000004 || RO || [31:28] || 0x0 || Zero Padding
|-
| 0x80000004 || RO || [27:16] || || Scan Frame Counter
|-
| 0x80000004 || RO || [15:8] || 0x0 || Zero Padding
|-
| 0x80000004 || RO || [7:0] || || Current Events
|}
{| class="wikitable" style="text-align:center"
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description
|+ 0x800xxxxx Scan Generator  (Read/Write Data)
|-
| 0x80000100 || RW || [27:16] || 0x000 || Total Height
|-
| 0x80000100  || RW || [11:0] || 0x000 || Total Width
|-
|. ||. ||. ||. ||.
|-
| 0x80000104 || RW || [11:0] || 0x000 || Total Frames
|-
|. ||. ||. ||. ||.
|-
| 0x80000108 || RW || [27:16] || 0x000 || Hor. Display End
|-
| 0x80000108 || RW || [11:0] || 0x000 || Hor. Display Start
|-
|. ||. ||. ||. ||.
|-
| 0x8000010C || RW || [27:16] || 0x000 || Vert. Display End
|-
| 0x8000010C || RW || [11:0] || 0x000 || Vert. Display Start
|-
|. ||. ||. ||. ||.
|-
| 0x80000110 || RW || [27:16] || 0x000 || Hor. Sync End
|-
| 0x80000110 || RW || [11:0] || 0x000 || Hor. Sync Start
|-
|. ||. ||. ||. ||.
|-
| 0x80000114 || RW || [27:16] || 0x000 || Vert. Sync End
|-
| 0x80000114 || RW || [11:0] || 0x000 || Vert. Sync Start
|-
|. ||. ||. ||. ||.
|-
| 0x80000118 || RW || [27:16] || 0x000 || Hor. Data End
|-
| 0x80000118 || RW || [11:0] || 0x000 || Hor. Data Start
|-
|. ||. ||. ||. ||.
|-
| 0x8000011C || RW || [27:16] || 0x000 || Vert. Data End
|-
| 0x8000011C || RW || [11:0] || 0x000 || Vert. Data Start
|-
|. ||. ||. ||. ||.
|-
| 0x80000120 || RW || [27:16] || 0x000 || Event Location 1 (Hor)
|-
| 0x80000120 || RW || [11:0] || 0x000 || Event Location 0 (Hor)
|-
|. ||. ||. ||. ||.
|-
| 0x80000124 || RW || [27:16] || 0x000 || Event Location 3 (Hor)
|-
| 0x80000124 || RW || [11:0] || 0x000 || Event Location 2 (Hor)
|-
|. ||. ||. ||. ||.
|-
| 0x80000128 || RW || [27:16] || 0x000 || Event Location 5 (Vert)
|-
| 0x80000128 || RW || [11:0] || 0x000 || Event Location 4 (Vert)
|-
|. ||. ||. ||. ||.
|-
| 0x8000012C || RW || [27:16] || 0x000 || Event Location 7 (Vert)
|-
| 0x8000012C || RW || [11:0] || 0x000 || Event Location 6 (Vert)
|-
|. ||. ||. ||. ||.
|-
| 0x80000130 || RW || [31:24] || 0x00 || Event 3 Configuration
|-
| 0x80000130 || RW || [23:16] || 0x00 || Event 2 Configuration
|-
| 0x80000130 || RW || [15:8] || 0x00 || Event 1 Configuration
|-
| 0x80000130 || RW || [7:0] || 0x00 || Event 0 Configuration
|-
|. ||. ||. ||. ||.
|-
| 0x80000134 || RW || [31:24] || 0x00 || Event 7 Configuration
|-
| 0x80000134 || RW || [23:16] || 0x00 || Event 6 Configuration
|-
| 0x80000134 || RW || [15:8] || 0x00 || Event 5 Configuration
|-
| 0x80000134 || RW || [7:0] || 0x00 || Event 4 Configuration
|-
|. ||. ||. ||. ||.
|-
| 0x80000138 || RW ||  [5] || 0 || Clip Range Overflow
|-
| 0x80000138 || RW ||  [4] || 0 || Clip Range Underflow
|-
| 0x80000138 || RW ||  [0] || 0 || Even/Odd Swap
|}
----
[[Category:Registers]]
[[Category:Memory]]
[[Category:CMV12000]]
[[Category:Sensors]]

Latest revision as of 08:28, 20 February 2024

Image Sensors main page


Sensor Pipeline

Address Description
0x600xxxxx CMV SPI register mapping
0x601xxxxx Capture Control/Address Gen.
0x602xxxxx LVDS input delay registers
0x603xxxxx RCN noise correction LUTs
0x604xxxxx CMV/AXI PLL dynalic reconf (disabled)
0x605xxxxx Linearization LUTs



Address Description
Display Pipeline
0x800xxxxx Display Scan Generator
0x801xxxxx Display Control/Address Gen.
0x802xxxxx Component Matrix 4x4
0x803xxxxx Gamma Correction LUTs
0x804xxxxx HDMI PLL dynamic reconf
0x805xxxxx Illumination Control (testing)



Address Type Bits Description
0x600xxxxx CMV SPI Register Mapping
0x60000000 RW [15:0] CMV Register 0
0x60000004 RW [15:0] CMV Register 1
.......... ...... ..............
0x600001F8 RW [15:0] CMV Register 126
0x600001FC RO [15:0] CMV Register 127



Address Type Bits Default Value Description
0x601xxxxx Capture Control/Address Gen. (Read Only Data)
0x60100000 RO [31:8] 0x524547 Identifier "REG"
0x60100000 RO [7:4] 0x0 Revision 0
0x60100000 RO [3:0] 0x8 Split x0100
. . . . .
0x60100004 RO [31:0] User Access
. . . . .
0x60100008 RO [31:0] LVDS Match (ch 0-31)
. . . . .
0x6010000C RO [31:0] LVDS Mismatch (ch 0-31)
. . . . .
0x60100010 RO [31:0] Current Writer Address
. . . . .
0x60100014 RO [31:30] Write Buffer Selection
0x60100014 RO [29:28] 0x0 Zero Padding
0x60100014 RO [27:24] Writer Inactive (0-3)
0x60100014 RO [23:22] 0x0 Zero Padding
0x60100014 RO [21] Fifo Write Error
0x60100014 RO [20] Fifo Read Error
0x60100014 RO [19] Fifo Full
0x60100014 RO [18] Fifo High
0x60100014 RO [17] Fifo Low
0x60100014 RO [16] Fifo Empty
0x60100014 RO [15:13] 0x0 Zero Padding
0x60100014 RO [12] Button Down State
0x60100014 RO [11] Button Up State
0x60100014 RO [10] Button Right State
0x60100014 RO [9] Button Left State
0x60100014 RO [8] Button Center State
0x60100014 RO [7:0] Switch State (0-7)
. . . . .
0x60100018 RO [31] Capture Sequence Drone
0x60100018 RO [30:28] Zero Padding
0x60100018 RO [27:16] CSeq Frame Count
0x60100018 RO [15:0] Zero Padding



Address Type Bits Default Value Description
0x601xxxxx Capture Control/Address Gen. (Read/Write Data)
0x60100100 RW [31:0] 0x18000000 Write Buffer 0 Base
0x60100104 RW [31:0] 0x19FF0000 Write Buffer 0 End Pattern
. . . . .
0x60100108 RW [31:0] 0x1A000000 Write Buffer 1 Base
0x6010010C RW [31:0] 0x1BFF0000 Write Buffer 1 End Pattern
. . . . .
0x60100110 RW [31:0] 0x1C000000 Write Buffer 2 Base
0x60100114 RW [31:0] 0x1DFF0000 Write Buffer 2 End Pattern
. . . . .
0x60100118 RW [31:0] 0x1E000000 Write Buffer 3 Base
0x6010011C RW [31:0] 0x1FFF0000 Write Buffer 3 End Pattern
. . . . .
0x60100120 RW [31:0] 0x00000080 Column Increment
. . . . .
0x60100124 RW [31:0] 0x00000080 Row Increment
. . . . .
0x60100128 RW [11:0] 0x0000007E Column Burst Count
. . . . .
0x6010012C RW [31:24] 0xFC Write Address Strobe
0x6010012C RW [21] 0x1 RCN Clip Overflow
0x6010012C RW [20] 0x1 RCN Clip Underflow
0x6010012C RW [19:16] 0xF Writer Enable
0x6010012C RW [15:12] 0xF Buffer Enable
0x6010012C RW [8] 0x0 SerDes Reset
0x6010012C RW [7] 0x0 Buffer Switch Request
0x6010012C RW [6] 0x0 Buffer Load Request
0x6010012C RW [5] 0x0 Buffer Reset Request
0x6010012C RW [4] 0x0 Buffer Block Request
0x6010012C RW [0] 0x0 Fifo Reset
. . . . .
0x60100130 RW [11:0] 0xA95 LVDS Training Pattern
. . . . .
0x60100134 RW [18:16] 0x07 Active Data Mask
0x60100134 RW [10:8] 0x07 Capture Data Mask
0x60100134 RW [2:0] 0x07 Capture Data Value
. . . . .
0x60100138 RW [23:16] 0x00 LED Override Mask (0-7)
0x60100138 RW [8] 0x0 Done LED Value
0x60100138 RW [7] 0x00 LED Override Value (0-7)
. . . . .
0x6010013C RW [28] 0x0 Button Down Override Enable
0x6010013C RW [27] 0x0 Button Up Override Enable
0x6010013C RW [26] 0x0 Button Right Override Enable
0x6010013C RW [25] 0x0 Button Left Override Enable
0x6010013C RW [24] 0x0 Button Center Override Enable
0x6010013C RW [23:16] 0x00 Switch Override Enable (0-7)
0x6010013C RW [12] 0x0 Button Down Override
0x6010013C RW [11] 0x0 Button Up Override
0x6010013C RW [10] 0x0 Button Right Override
0x6010013C RW [9] 0x0 Button Left Override
0x6010013C RW [8] 0x0 Button Center Override
0x6010013C RW [7] 0x00 Switch Override (0-7)



Address Type Bits Default Value Description
0x602xxxxx LVDS Input Delay
0x60200000 WO [31] 0x0 Bitslip Channel 0
0x60200000 RO [29] Pattern Match Channel 0
0x60200000 RO [28] Pattern Mismatch Channel 0
0x60200000 RW [4:0] 0x0 Delay Value Channel 0
. . . . .
0x60200004 Same for Channel 1
.......... ..............
0x6020007C Same for Channel 31
0x60200080 Same for Control Channel
. . . . .
0x60200084 WO [31] 0x0 Word Slip/Phase for all Channels
0x60200084 RW [4:0] 0x0 Delay Value for LVDS Clock



Address Type Bits Default Value Description
0x6030xxxx Column Offset LUTs
0x60300000 RW [11:0] 0x000 Signed 12bit Offset (Column 0)
. . . . .
0x60300004 RW [11:0] 0x000 Signed 12bit Offset (Column 2)
0x60300008 RW [11:0] 0x000 Signed 12bit Offset (Column 4)
.......... ..............
0x60301FF8 RW [11:0] 0x000 Signed 12bit Offset (Column 4092)
0x60301FFC RW [11:0] 0x000 Signed 12bit Offset (Column 4094)
. . . . .
0x60302000 RW [11:0] 0x000 Signed 12bit Offset (Column 1)
. . . . .
0x60302004 RW [11:0] 0x000 Signed 12bit Offset (Column 3)
0x60302008 RW [11:0] 0x000 Signed 12bit Offset (Column 5)
.......... ..............
0x60303FF8 RW [11:0] 0x000 Signed 12bit Offset (Column 4093)
0x60303FFC RW [11:0] 0x000 Signed 12bit Offset (Column 4095)



Address Type Bits Default Value Description
0x6030xxxx Row Offset LUTs
0x60304000 RW [11:0] 0x000 Signed 12bit Offset (Row 0)
. . . . .
0x60304004 RW [11:0] 0x000 Signed 12bit Offset (Row 2)
0x60304008 RW [11:0] 0x000 Signed 12bit Offset (Row 4)
.......... ..............
0x60305FF8 RW [11:0] 0x000 Signed 12bit Offset (Row 4092)
0x60305FFC RW [11:0] 0x000 Signed 12bit Offset (Row 4094)
. . . . .
0x60306000 RW [11:0] 0x000 Signed 12bit Offset (Row 1)
. . . . .
0x60306004 RW [11:0] 0x000 Signed 12bit Offset (Row 3)
0x60306008 RW [11:0] 0x000 Signed 12bit Offset (Row 5)
.......... ..............
0x60307FF8 RW [11:0] 0x000 Signed 12bit Offset (Row 4093)
0x60307FFC RW [11:0] 0x000 Signed 12bit Offset (Row 4095)



Address Type Bits Default Value Description
0x6050xxxx Linearization LUTs
0x60500000 RW [17:0] 0x0000 Signed 18bit (Chan 0, Val 0)
. . . . .
0x60500004 RW [17:0] 0x0000 Signed 18bit (Chan 0, Val 1)
.......... ..............
0x60503FFC RW [17:0] 0x0000 Signed 18bit (Chan 0, Val 4095)
. . . . .
0x60504000 RW [17:0] 0x0000 Signed 18bit (Chan 1, Val 0)
. . . . .
0x60504004 RW [17:0] 0x0000 Signed 18bit (Chan 1, Val 1)
.......... ..............
0x60507FFC RW [17:0] 0x0000 Signed 18bit (Chan 1, Val 4095)
. . . . .
0x60508000 RW [17:0] 0x0000 Signed 18bit (Chan 2, Val 0)
. . . . .
0x60508004 RW [17:0] 0x0000 Signed 18bit (Chan 2, Val 1)
.......... ..............
0x6050BFFC RW [17:0] 0x0000 Signed 18bit (Chan 2, Val 4095)
. . . . .
0x6050C000 RW [17:0] 0x0000 Signed 18bit (Chan 3, Val 0)
. . . . .
0x6050C004 RW [17:0] 0x0000 Signed 18bit (Chan 3, Val 1)
.......... ..............
0x6050FFFC RW [17:0] 0x0000 Signed 18bit (Chan 3, Val 4095)



Address Type Bits Default Value Description
0x800xxxxx Scan Generator (Read Only Data)
0x80000000 RO [31:8] 0x53434E Identifier "SCN"
0x80000000 RO [7:4] 0x0 Revision 0
0x80000000 RO [3:0] 0x8 Split x0100
. . . . .
0x80000004 RO [31:28] 0x0 Zero Padding
0x80000004 RO [27:16] Scan Frame Counter
0x80000004 RO [15:8] 0x0 Zero Padding
0x80000004 RO [7:0] Current Events



Address Type Bits Default Value Description
0x800xxxxx Scan Generator (Read/Write Data)
0x80000100 RW [27:16] 0x000 Total Height
0x80000100 RW [11:0] 0x000 Total Width
. . . . .
0x80000104 RW [11:0] 0x000 Total Frames
. . . . .
0x80000108 RW [27:16] 0x000 Hor. Display End
0x80000108 RW [11:0] 0x000 Hor. Display Start
. . . . .
0x8000010C RW [27:16] 0x000 Vert. Display End
0x8000010C RW [11:0] 0x000 Vert. Display Start
. . . . .
0x80000110 RW [27:16] 0x000 Hor. Sync End
0x80000110 RW [11:0] 0x000 Hor. Sync Start
. . . . .
0x80000114 RW [27:16] 0x000 Vert. Sync End
0x80000114 RW [11:0] 0x000 Vert. Sync Start
. . . . .
0x80000118 RW [27:16] 0x000 Hor. Data End
0x80000118 RW [11:0] 0x000 Hor. Data Start
. . . . .
0x8000011C RW [27:16] 0x000 Vert. Data End
0x8000011C RW [11:0] 0x000 Vert. Data Start
. . . . .
0x80000120 RW [27:16] 0x000 Event Location 1 (Hor)
0x80000120 RW [11:0] 0x000 Event Location 0 (Hor)
. . . . .
0x80000124 RW [27:16] 0x000 Event Location 3 (Hor)
0x80000124 RW [11:0] 0x000 Event Location 2 (Hor)
. . . . .
0x80000128 RW [27:16] 0x000 Event Location 5 (Vert)
0x80000128 RW [11:0] 0x000 Event Location 4 (Vert)
. . . . .
0x8000012C RW [27:16] 0x000 Event Location 7 (Vert)
0x8000012C RW [11:0] 0x000 Event Location 6 (Vert)
. . . . .
0x80000130 RW [31:24] 0x00 Event 3 Configuration
0x80000130 RW [23:16] 0x00 Event 2 Configuration
0x80000130 RW [15:8] 0x00 Event 1 Configuration
0x80000130 RW [7:0] 0x00 Event 0 Configuration
. . . . .
0x80000134 RW [31:24] 0x00 Event 7 Configuration
0x80000134 RW [23:16] 0x00 Event 6 Configuration
0x80000134 RW [15:8] 0x00 Event 5 Configuration
0x80000134 RW [7:0] 0x00 Event 4 Configuration
. . . . .
0x80000138 RW [5] 0 Clip Range Overflow
0x80000138 RW [4] 0 Clip Range Underflow
0x80000138 RW [0] 0 Even/Odd Swap


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