Difference between revisions of "USB 3.0 Plugin Module Gearwork"
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== Project Summary == | == Project Summary == | ||
The AXIOM Beta currently features PCIe x1 connectors on the | The AXIOM Beta currently features PCIe x1 connectors on the mainboard which are capable of transferring data at a rate of 6Gbit/s or more. Several high-speed plugin modules like HDMI, DP, or SDI can be plugged into these, thereby providing additional functionalities. The AXIOM Beta lacked an USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. In this project, I wrote all the HDL code for gearwork of the USB 3.0 plugin module (designed by apertus°) so that it can transfer live 4K video data at 20+ FPS from the LVDS lanes exposed by the PCIe connectors on AXIOM Beta main board to the connected PC by use of an USB 3.0 port. | ||
'''Google Summer of Code 2019 project.''' | '''Google Summer of Code 2019 project.''' | ||
''Mentored by:'' '''Bertl''' | |||
''Implemented by:'' '''Apurva Nandan''' | |||
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== Important Links == | |||
* [https://github.com/apurvanandan1997/usb_plug_mod_ber GSoC'19 Source Code] | |||
* [https://github.com/apurvanandan1997/usb_plug_mod_ber | * [https://github.com/apurvanandan1997/usb_plug_mod_ber/blob/master/GSoC19_Report.pdf GSoC'19 Project Report] | ||
* [https://github.com/apurvanandan1997/SerDes_T871_A/blob/master/Proposal/Apertus_USB_3.0_GearWork_Project_Proposal.pdf Proposal] | * [https://github.com/apurvanandan1997/SerDes_T871_A/blob/master/Proposal/Apertus_USB_3.0_GearWork_Project_Proposal.pdf GSoC'19 Project Proposal] | ||
* [https:// | * [https://summerofcode.withgoogle.com/projects/#4870344697970688 GSoC'19 Project Page] | ||
* [https:// | * [https://lab.apertus.org/T885 Apertus° Lab Task T885 ] | ||
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== References == | == References == | ||
* [https://wiki.apertus.org/index.php/1x_USB_3.0_Plugin_Module USB 3.0 Plugin Module Wiki ] | * [https://wiki.apertus.org/index.php/1x_USB_3.0_Plugin_Module USB 3.0 Plugin Module Hardware Wiki ] | ||
* [https://www.latticesemi.com/Products/FPGAandCPLD/MachXO2 Lattice MachXO2 FPGA] | * [https://www.latticesemi.com/Products/FPGAandCPLD/MachXO2 Lattice MachXO2 FPGA] | ||
Latest revision as of 16:06, 25 August 2019
1 Project Summary
The AXIOM Beta currently features PCIe x1 connectors on the mainboard which are capable of transferring data at a rate of 6Gbit/s or more. Several high-speed plugin modules like HDMI, DP, or SDI can be plugged into these, thereby providing additional functionalities. The AXIOM Beta lacked an USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. In this project, I wrote all the HDL code for gearwork of the USB 3.0 plugin module (designed by apertus°) so that it can transfer live 4K video data at 20+ FPS from the LVDS lanes exposed by the PCIe connectors on AXIOM Beta main board to the connected PC by use of an USB 3.0 port.
Google Summer of Code 2019 project.
Mentored by: Bertl
Implemented by: Apurva Nandan