Difference between revisions of "CMV12000 Register Blocks"
Line 96: | Line 96: | ||
! Type | ! Type | ||
! Bits | ! Bits | ||
! Default Values | |||
! Capture Control / Address Gen. | ! Capture Control / Address Gen. | ||
|- | |- | ||
Line 102: | Line 103: | ||
RO | RO | ||
<br>RO | <br>RO | ||
| [31:8] | | [31:8] | ||
[7:4] | [7:4] | ||
<br>[3:0] 0x8 | <br>[3:0] | ||
| 0x524547 | |||
0x0 | |||
<br> 0x8 | |||
| Identifier "REG" | | Identifier "REG" | ||
Revision 0 | Revision 0 | ||
Line 112: | Line 116: | ||
| RO | | RO | ||
| [31:0] | | [31:0] | ||
| | |||
| User Access | | User Access | ||
|- | |- | ||
Line 117: | Line 122: | ||
| RO | | RO | ||
| [31:0] | | [31:0] | ||
| | |||
| LVDS Match (ch 0-31) | | LVDS Match (ch 0-31) | ||
|- | |- | ||
Line 122: | Line 128: | ||
| RO | | RO | ||
| [31:0] | | [31:0] | ||
| | |||
| LVDS Mismatch (ch 0-31) | | LVDS Mismatch (ch 0-31) | ||
|- | |- | ||
Line 127: | Line 134: | ||
| RO | | RO | ||
| [31:0] | | [31:0] | ||
| | |||
| Current Writer Address | | Current Writer Address | ||
|- | |- | ||
Line 148: | Line 156: | ||
<br> RO | <br> RO | ||
|[31:30] | |[31:30] | ||
[29:28] | [29:28] | ||
<br> [27:24] | <br> [27:24] | ||
<br> [23:22] | <br> [23:22] | ||
<br> [21] | <br> [21] | ||
<br> [20] | <br> [20] | ||
Line 157: | Line 165: | ||
<br> [17] | <br> [17] | ||
<br> [16] | <br> [16] | ||
<br> [15:13] | <br> [15:13] | ||
<br> [12] | <br> [12] | ||
<br> [11] | <br> [11] | ||
Line 164: | Line 172: | ||
<br> [8] | <br> [8] | ||
<br> [7:0] | <br> [7:0] | ||
| | |||
0x0 | |||
<br> | |||
<br> 0x0 | |||
<br> | |||
<br> | |||
<br> | |||
<br> | |||
<br> | |||
<br> | |||
<br> 0x0 | |||
<br> | |||
<br> | |||
<br> | |||
<br> | |||
<br> | |||
<br> | |||
| Write Buffer Selection | | Write Buffer Selection | ||
Zero Padding | Zero Padding | ||
Line 191: | Line 216: | ||
<br> [27:16] | <br> [27:16] | ||
<br> [15:0] | <br> [15:0] | ||
| | |||
| Capture Sequencer Done | | Capture Sequencer Done | ||
Zero Padding | Zero Padding |
Revision as of 23:59, 13 March 2014
Sensor Pipeline
Address | Description |
---|---|
0x600xxxxx | CMV SPI register mapping |
0x601xxxxx | Capture Control/Address Gen. |
0x602xxxxx | LVDS input delay registers |
0x603xxxxx | RCN noise correction LUTs |
0x604xxxxx | CMV/AXI PLL dynalic reconf (disabled) |
0x605xxxxx | Linearization LUTs |
Display Pipeline
Address | Description |
---|---|
0x800xxxxx | Display Scan Generator |
0x801xxxxx | Display Control/Address Gen. |
0x802xxxxx | Component Matrix 4x4 |
0x803xxxxx | Gamma Correction LUTs |
0x804xxxxx | HDMI PLL dynamic reconf |
0x805xxxxx | Illumination Control (testing) |
0x600xxxxx CMV SPI register mapping
Address | Type | Bits | Description |
---|---|---|---|
0x60000000 | RW | [15:0] | CMV Register 0 |
0x60000004 | RW | [15:0] | CMV Register 1 |
.......... | ...... | .............. | |
0x600001F8 | RW | [15:0] | CMV Register 126 |
0x600001FC | RO | [15:0] | CMV Register 127 |
0x601xxxxx Capture Control/Address Gen. (Read Only Data)
Address | Type | Bits | Default Values | Capture Control / Address Gen. |
---|---|---|---|---|
0x60100000 | RO
RO
|
[31:8]
[7:4]
|
0x524547
0x0
|
Identifier "REG"
Revision 0
|
0x60100004 | RO | [31:0] | User Access | |
0x60100008 | RO | [31:0] | LVDS Match (ch 0-31) | |
0x6010000C | RO | [31:0] | LVDS Mismatch (ch 0-31) | |
0x60100010 | RO | [31:0] | Current Writer Address | |
0x60100014 | RO
RO
|
[31:30]
[29:28]
|
0x0
|
Write Buffer Selection
Zero Padding
|
0x60100018 | RO
RO
|
[31]
[30:28]
|
Capture Sequencer Done
Zero Padding
|
0x601xxxxx Capture Control/Address Gen. (Read/Write Data)
Address | Type | Bits | Capture Control / Address Gen. | Description |
---|---|---|---|---|
0x60100100
0x60100104 |
RW
RW |
[31:0]
[31:0] |
0x18000000
0x19FF0000 |
Write Buffer 0 Base
Write Buffer 0 End Pattern |
0x60100108
0x6010010C |
RW
RW |
[31:0]
[31:0] |
0x1A000000
0x1BFF0000 |
Write Buffer 1 Base
Write Buffer 1 End Pattern |
0x60100110
0x60100114 |
RW
RW |
[31:0]
[31:0] |
0x1C000000
0x1DFF0000 |
Write Buffer 2 Base
Write Buffer 2 End Pattern |
0x60100118
0x6010011C |
RW
RW |
[31:0]
[31:0] |
0x1E000000
0x1FFF0000 |
Write Buffer 3 Base
Write Buffer 3 End Pattern |
0x60100120 | RW | [31:0] | 0x00000080 | Column Increment |
0x60100124 | RW | [31:0] | 0x00000080 | Row Increment |
0x60100128 | RW | [11:0] | 0x0000007E | Column Burst Count |
0x6010012C | RW
RW
|
[31:24] 0xFC
[21] 0x1
|
Write Address Strobe
RCN Clip Overflow
| |
0x60100130 | RW | [11:0] 0xA95 | LVDS Training Pattern | |
0x60100134 | RW
RW
|
[18:16] 0x07
[10:8] 0x07
|
Active Data Mask
Capture Data Mask
| |
0x60100138 | RW
RW
|
[23:16] 0x00
[8] 0x0
|
LED Override Mask (0-7)
Done LED Value
| |
0x6010013C | RW
RW
|
[28] 0x0
[27] 0x0
|
Button Down Override Enable
Button Up Override Enable
|