Difference between revisions of "USB 3.0 Plugin Module Gearwork"
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== Important URLs == | == Important URLs == | ||
- | - [https://github.com/apurvanandan1997/usb_plug_mod_ber Code] | ||
- Proposal [https://github.com/apurvanandan1997/SerDes_T871_A/blob/master/Proposal/Apertus_USB_3.0_GearWork_Project_Proposal.pdf] | - Proposal [https://github.com/apurvanandan1997/SerDes_T871_A/blob/master/Proposal/Apertus_USB_3.0_GearWork_Project_Proposal.pdf] | ||
Revision as of 17:19, 23 August 2019
PAGE UNDER CONSTRUCTION
1 Project Summary
The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gbit/s or more. Several high speed plugin modules like HDMI, DP or SDI can be plugged into these thereby providing additional functionalities.Currently, the AXIOM Beta lacks a USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. This project is about implementing a USB 3.0 gearwork using the LVDS connection exposed by the PCIe connectors for streaming 4K 12-bit video at 25 FPS. There is no aftermarket solutions for high speed LVDS to USB 3.0 conversion. Only 16/24/32-bit parallel data to USB 3.0 bridges are available. Hence, a USB 3.0 plugin module has been designed by apertus° featuring a MachXO2 Lattice FPGA and FT601Q/FT602 FTDI IC for this purpose.
Google Summer of Code 2019 project.
Mentored by: Bertl.
Implemented by: Apurva Nandan
2 Important URLs
- Code
- Proposal [1]
- Report [2]
- Project Page at GSoC'19 [3]
- Lab Task [4]
3 References
- USB 3.0 Plugin Module Wiki [5]
- Lattice MachXO2 FPGA [6]
- Implementing High-Speed Interfaces with MachXO2 Devices - TN1203 [7]
- FTDI FT601Q chip [8]