Difference between revisions of "CMV12000 Register Blocks"
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{| class="wikitable" | {| class="wikitable" style="text-align:center" | ||
!class="reg"| Address || class="reg"| Type || class="reg"| Bits || class="reg"| Default Value || class="reg"| Description | |||
|+ 0x601xxxxx Capture Control/Address Gen. (Read Only Data) | |+ 0x601xxxxx Capture Control/Address Gen. (Read Only Data) | ||
|- | |- | ||
| 0x60100000 || RO <br> RO <br> RO || [31:8] <br> [7:4] <br>[3:0] || 0x524547 <br> 0x0 <br> 0x8 || Identifier "REG" <br> Revision 0 <br> Split x0100 | |||
|- | |- | ||
| | | 0x60100004 || RO || [31:0] || || User Access | ||
| RO | |||
| [31 | |||
| | |||
| | |||
| | |||
| User Access | |||
|- | |- | ||
| 0x60100008 | | 0x60100008 || RO || [31:0] || || LVDS Match (ch 0-31) | ||
| RO | |- | ||
| [31:0] | | 0x6010000C || RO || [31:0] || || LVDS Mismatch (ch 0-31) | ||
| | |||
| LVDS Match (ch 0-31) | |||
|- | |||
| 0x6010000C | |||
| RO | |||
| [31:0] | |||
| | |||
| LVDS Mismatch (ch 0-31) | |||
|- | |- | ||
| 0x60100010 | | 0x60100010 || RO || [31:0] || || Current Writer Address | ||
| RO | |- | ||
| [31:0] | | 0x60100014 || | ||
| | RO | ||
| Current Writer Address | <br> RO | ||
|- | |||
| 0x60100014 | |||
RO | |||
<br> RO | <br> RO | ||
<br> RO | <br> RO | ||
Line 134: | Line 101: | ||
<br> RO | <br> RO | ||
<br> RO | <br> RO | ||
|[31:30] | || [31:30] | ||
[29:28] | [29:28] | ||
<br> [27:24] | <br> [27:24] | ||
Line 151: | Line 118: | ||
<br> [8] | <br> [8] | ||
<br> [7:0] | <br> [7:0] | ||
| | || 0x0 | ||
0x0 | |||
<br> | <br> | ||
<br> 0x0 | <br> 0x0 | ||
Line 168: | Line 134: | ||
<br> | <br> | ||
<br> | <br> | ||
| Write Buffer Selection | <br> | ||
|| Write Buffer Selection | |||
Zero Padding | Zero Padding | ||
<br> Writer Inactive (0-3) | <br> Writer Inactive (0-3) | ||
Line 186: | Line 153: | ||
<br> Switch State (0-7) | <br> Switch State (0-7) | ||
|- | |- | ||
| 0x60100018 | | 0x60100018 || RO <br> RO<br> RO <br> RO ||[31] <br> [30:28] <br> [27:16] <br> [15:0] || || Capture Sequencer Done <br> Zero Padding <br> CSeq Frame Count <br> Zero Padding | ||
| RO | |||
RO | |||
<br> RO | |||
<br> RO | |||
|[31] | |||
[30:28] | |||
<br> [27:16] | |||
<br> [15:0] | |||
| | |||
| Capture Sequencer Done | |||
Zero Padding | |||
<br> CSeq Frame Count | |||
<br> Zero Padding | |||
|} | |} | ||
Revision as of 06:29, 31 March 2014
1 CMV12000 Register Blocks
1.1 Sensor Pipeline
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td.odd { color:#F00 } td.even { color:#000 }
</css>
Address | Description |
---|---|
0x600xxxxx | CMV SPI register mapping |
0x601xxxxx | Capture Control/Address Gen. |
0x602xxxxx | LVDS input delay registers |
0x603xxxxx | RCN noise correction LUTs |
0x604xxxxx | CMV/AXI PLL dynalic reconf (disabled) |
0x605xxxxx | Linearization LUTs |
Address | Description |
---|---|
0x800xxxxx | Display Scan Generator |
0x801xxxxx | Display Control/Address Gen. |
0x802xxxxx | Component Matrix 4x4 |
0x803xxxxx | Gamma Correction LUTs |
0x804xxxxx | HDMI PLL dynamic reconf |
0x805xxxxx | Illumination Control (testing) |
Address | Type | Bits | Description |
---|---|---|---|
0x60000000 | RW | [15:0] | CMV Register 0 |
0x60000004 | RW | [15:0] | CMV Register 1 |
.......... | ...... | .............. | |
0x600001F8 | RW | [15:0] | CMV Register 126 |
0x600001FC | RO | [15:0] | CMV Register 127 |
Address | Type | Bits | Default Value | Description |
---|---|---|---|---|
0x60100000 | RO RO RO |
[31:8] [7:4] [3:0] |
0x524547 0x0 0x8 |
Identifier "REG" Revision 0 Split x0100 |
0x60100004 | RO | [31:0] | User Access | |
0x60100008 | RO | [31:0] | LVDS Match (ch 0-31) | |
0x6010000C | RO | [31:0] | LVDS Mismatch (ch 0-31) | |
0x60100010 | RO | [31:0] | Current Writer Address | |
0x60100014 |
RO
|
[31:30]
[29:28]
|
0x0
|
Write Buffer Selection
Zero Padding
|
0x60100018 | RO RO RO RO |
[31] [30:28] [27:16] [15:0] |
Capture Sequencer Done Zero Padding CSeq Frame Count Zero Padding |
Address | Type | Bits | Default Value | Description |
---|---|---|---|---|
0x60100100
0x60100104 |
RW
RW |
[31:0]
[31:0] |
0x18000000
0x19FF0000 |
Write Buffer 0 Base
Write Buffer 0 End Pattern |
0x60100108
0x6010010C |
RW
RW |
[31:0]
[31:0] |
0x1A000000
0x1BFF0000 |
Write Buffer 1 Base
Write Buffer 1 End Pattern |
0x60100110
0x60100114 |
RW
RW |
[31:0]
[31:0] |
0x1C000000
0x1DFF0000 |
Write Buffer 2 Base
Write Buffer 2 End Pattern |
0x60100118
0x6010011C |
RW
RW |
[31:0]
[31:0] |
0x1E000000
0x1FFF0000 |
Write Buffer 3 Base
Write Buffer 3 End Pattern |
0x60100120 | RW | [31:0] | 0x00000080 | Column Increment |
0x60100124 | RW | [31:0] | 0x00000080 | Row Increment |
0x60100128 | RW | [11:0] | 0x0000007E | Column Burst Count |
0x6010012C | RW
RW
|
[31:24]
[21]
|
0xFC
0x1
|
Write Address Strobe
RCN Clip Overflow
|
0x60100130 | RW | [11:0] | 0xA95 | LVDS Training Pattern |
0x60100134 | RW
RW
|
[18:16]
[10:8]
|
0x07
0x07
|
Active Data Mask
Capture Data Mask
|
0x60100138 | RW
RW
|
[23:16]
[8]
|
0x00
0x0
|
LED Override Mask (0-7)
Done LED Value
|
0x6010013C | RW
RW
|
[28]
[27]
|
0x0
0x0
|
Button Down Override Enable
Button Up Override Enable
|