AXIOM Alpha

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1 About

Officially website: http://axiom.apertus.org/index.php?site=alpha

2 Task Management

List of Axiom Alpha Prototype Development Tasks

might be incomplete - add more tasks as needed at the proper stage



Sensor board hardware : pcb design, building, soldering, sensor, test, iterative process


Create a general timing framework, having in mind the higher framerate, communication between FPGA and CPU through circular image buffer in shared memory, sensor requirements regarding timing when grabbing one frame.


Sensor initialization : Logic/Drivers to boot the image sensor (run startup sequence). Put the sensor in the right mode for our use (exposure, resolution, etc).


IP Core that reads LVDS data from CMV12000 , putting pixels into correct order and putting them into memory for each image


Circular image buffer tests / design: How to share the images from the sensor in memory between FPGA and CPU? Do we need a memory Controller (DDR3 memory) for DMA (FPGA/CPU) or does the Zedboard contain one off-the-shelf already? How much memory is needed for embedded linux vs FPGA memory needed to have a decent circular image buffer (how many frames should we store in memory [one image at full resolution/12 bit has 18.874,368 bytes]).


Linux drivers to set/get CMV12000 sensor registers via Linux command-line on Zedboard plus demo script/program (SPI interface to sensor)


IP Core that crops the 4K bayer pattern to 3840x2160 photosites and then down-samples to 1920x1080 (Full HD) RGB from bayer pattern using a simplified method in real-time (25FPS) (see picture)


IP Core that applies per-channel-factors (R, G, B) to an image of arbitrary resolution/bit-depth for Whitebalance correction with minimal latency (real time)


IP Core that applies Gamma Curve to an image of arbitrary resolution for 12 bit to 8 bit per channel conversion with minimal latency (real time)


IP Core or Glue logic that outputs the processed video stream over the Zedboards HDMI connector in 1080p25 (this could be done on the linux side providing the 2 cores are fast enough)


Better debayersiation (later)


Dead pixel removal (later)


Fixed pattern noise (later)


Dig the options for recording :

  • fpga sata core? Linux -> DMA <- fpga => use linux to write trough sata / usb / wathever (filesystem, file format (DNGheaders) handled by linux, one core for image processing, the other for file writing?)
  • Custom flash media
  • Built-in compression and write to a lower end device?
  • What will user want for recording? (file format and media)



Make tests with various linux distributions available for the zedboard, see which one fits best, test memory consumption, speed test on ram, dma, custom linux distribution needed ? How to provide everything on an SD card (later)


Provide a way to update the FPGA using the SD card with the linux system (kind of firmware upgrade for dummies)


Consider if still required: Emulated CMV12000 IP Core (image sensor at full resolution 12 bit bayer pattern (4096x3072) 25 FPS with a simple moving video loop (spinning line for example) and the CMV12000 registers set/get-able over SPI with dummy data (link exposure time to color of spinning line for example so we can verify register access is working)

3 Zedboard related Notes

3.1 Zedboard Development on Ubuntu 12.04 LTS with ISE 14.5 (Currently running in Virtual Box on a Mac)

Plug in two micro USB cables (one is provided with the Zedboard) to Zedboard ports J13 and J17 (UART and PROG) respectively. Set jumpers JP7-JP11 as described in tutorial for Helloworld. Plug USB cables into computer.

Turn on Zedboard. In Virtual Box open the machine settings that Ubuntu is installed in. Select the Ports tab, and the USB tab. Add a USB Device Filter (plus sign) for 2012 Cyprus Semiconductor Cypress - USB2UART-Ver1.0G, and also Digilent USB Device. This automatically connects the USB ports for Ubuntu whenever the Zedboard is connected.

In Ubuntu:


Note, to extract files use: tar -xvf filename


1) Install libusb: sudo apt-get install libusb-dev

2) Work around for arm toolchain install: sudo dpkg-reconfigure -plow dash (Select NO when prompted)

3) Download ISE 14.5

4) Install: ./xsetup (do not install cable drivers). Select System Edition

5) Work around for arm toolchain install: sudo dpkg-reconfigure -plow dash (Select YES when prompted)

6) Download Digilent Runtime and Utilities: [1]

7) Install both using: sudo ./install.sh (note install can be for all users or the user installing, see README for instructions)

8) Download Digilent Plugin: [2]

9) Install plugin per instructions included in PDF.


Note there are several terminal emulator options. Minicom can be run in a shell. A google search will show how to use it. Alternatively in SDK you can use the terminal emulator that is included.

3.2 Getting JTAG working with the Zedboard

From http://www.digilentinc.com/Products/Detail.cfm?NavPath=2%2C66%2C828&Prod=ADEPT2 download the following packages (these are for 64bit so for x86 you will want the 32bit versions): 

digilent.adept.runtime_2.13.1-x86_64.tar.gz
digilent.adept.utilities_2.1.1-x86_64.tar.gz
libCseDigilent_2.4.3-x86_64.tar.gz

then install the runtime: 

tar xzf digilent.adept.runtime_2.13.1-x86_64.tar.gz; cd digilent.adept.runtime_2.13.1-x86_64; ./install.sh

and here is the important part: AND the ftdi driver 

cd ftdi.drivers_1.0.4-x86_64; ./install.sh

then the utilities 

same method as runtime above

at this point the following command 

djtgcfg enum

should show board details: 

Found 1 device(s)

Device: Zed
   Product Name:   Digilent Zed
   User Name:      Zed
   Serial Number:  XXXXXXXXXXXX

Note that you need to fix the udev rules, restart udev and unplug/replug the usb-jtag to get the driver (ftdi_sio) unloaded and the permissions for the usb device changed.

The libCseDigilent_2.4.3-x86_64.tar.gz contains two files in ISE14x/plugin: 

libCseDigilent.so  
libCseDigilent.xml

which need to be copied to the ISE plugin directory.

after that, the following should work: 

xmd

and should show something like: 

Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.5 Build EDK_P.58f
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Then typing: 

connect mb mdm -cable type xilinx_plugin modulename digilent_plugin

Should show: 

XMD%
XMD% connect mb mdm -cable type xilinx_plugin modulename digilent_plugin

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020
ERROR: Could not detect MDM peripheral on hardware. Please check:
        1. If FPGA is configured correctly
        2. MDM Core is instantiated in the design
        3. If the correct FPGA is referred, in case of multiple FPGAs
        4. If the correct MDM is referred, in case of a multiple MDM system

Note that the default image has no mdm IP

3.3 Booting the Zedboard via JTAG

You want to get the ZedBoard_CTT_v14.3_121017.zip for some files from: http://www.zedboard.org/sites/default/files/design/ZedBoard_CTT_v14.3_121017.zip namely: ps7_init.tcl and stub.tcl

Then you also need the following from your design:

  • system.bit [PL bitstream]
  • u-boot.elf or some other elf binary [PS 2nd stage]
  • optionally (Linux Boot): zImage, ramdisk*.gz and devicetree.dtb

start xmd (the Xilinx® Microprocessor Debugger console as part of ISE), then in the xmd prompt do: 

connect arm hw
fpga -f system.bit
source ps7_init.tcl
ps7_init
init_user
source stub.tcl
target 64
dow u-boot.elf
con

this will connect to the target, upload the fpga bitstream (PL), initialize memory and MIO devices (ps7_init/init_user) and load the second level bootloader (PS) the 'con' already starts the bootloader

optionally, you can also upload the Linux kernel, initramfs and the devicetree like this: 

dow -data zImage 0x8000
dow -data ramdisk8M.image.gz 0x800000
dow -data devicetree.dtb 0x1000000

and boot the kernel/linux with: 

con 0x8000


3.4 Booting the Zedboard via TFTP

Booting the Zedboard via TFTP is a lot faster than the JTAG boot method and doesn't have the drawbacks of SD card shuffling.

All you need to do is download boot.bin (as BOOT.BIN) and copy it the to the SD card or to flash:

Connect the Zedboard via Ethernet and have a DHCP/BOOTP and TFTP server running somewhere on the network.

You also want to copy the 'ZED' folder to your TFTP server.

Guides how to install/set up TFTP:

Typically you link the parts inside the ZED folder image on TFTP in the same dir like this: 

system.bin -> ZedBoard_OOB_Design/system.bin
ramdisk.image.gz -> ZedBoard_OOB_Design/ramdisk8M.image.gz
devicetree_ramdisk.dtb -> ZedBoard_OOB_Design/devicetree_ramdisk.dtb
zImage -> ZedBoard_OOB_Design/zImage

The boot.bin will request an IP and server via DPPTP/DHCP and then start loading the advertised boot file, which is an u-boot script which is then executed, and can be used to customize the setup steps an example script is provided to boot into the demo ZedBoard_OOB design.

3.4.1 Boot Process

Boot time from power on till Linux prompt is 29 seconds

5 seconds till boot.bin is booted, 3 seconds wait to interrupt the bootloader, 3 seconds kernel boot, rest is bootp/tftp and stuff

  1. Autoboot (from boot.bin) will first request an IP via BOOTP
  2. Then request the file ZED/u-boot.scr (the script)
  3. Then execute that script, which contains:
  4. tftp 0x1000000 ZED/system.bin
  5. fpga load 0 0x${fileaddr} 0x${filesize}
  6. tftp 0x8000 ZED/zImage
  7. tftp 0x1000000 ZED/devicetree_ramdisk.dtb
  8. tftp 0x800000 ZED/ramdisk.image.gz
  9. bootz 0x8000 0x${fileaddr}:0x${filesize} 0x1000000
  10. go 0x8000 so it first fetches the PL code and uploads it to the FPGA
  11. then it requests the kernel, devicetree and initrd
  12. then it tries to boot the new style

4 Sensor Front End

4.1 Parts

4.1.1 Image Sensor

CMV12000 from Cmosis

http://www.cmosis.com/products/standard_products/cmv12000

Price: 1265.00 €

4.1.2 FMC connector

Samtec Vita 57

http://www.samtec.com/standards/vita.aspx

Part Number: ASP-134604-01

Price: $19.70

4.1.3 HDR Cable

300mm FMC extension cable (HDR⁃169473⁃01)

http://www.samtec.com/standards/vita.aspx

Price: $180.54

4.1.4 Image Sensor Socket

Socket for CMV12000 from Andon:

Partnumber | Prices: 10-30-07-237-414T4-R27-L14 - 87.00 €

10-30-07-237-400T4-R27-L14 - 88.15 €

10-30-07-237-RB501T4-R27-L14 - 102.30 €


4.2 Reading and Writing Sensor Register

This example script: 

#!/bin/sh
cmv_reg() {
   addr=$(( 0x60000000 + ($1 * 4) ))
   [ $# -gt 1 ] && devmem $addr 32 $2
   devmem $addr 32
}
#change the registers 69/98/102/107/108/112 and 124                 
cmv_reg  69      2
cmv_reg  98  39705
cmv_reg 102   8312
cmv_reg 107   9814
cmv_reg 108  12381
cmv_reg 112      5
cmv_reg 124     15
#read the register 127
cmv_reg 127

basically the registers get mapped to 32bit spaces starting at a specific memory address (0x60000000 in this case), reading from that memory will show the register, writing to that memory will change it

so register '0' is at 0x60000000, register '1' at 0x60000004 ...


This example script reads the current bitdepth the sensor is running with: 

get_bitdepth () {
	depth=$(( `cmv_reg 118` + 0 ))
	[ $depth -eq 0 ] && echo "12 bit mode"
	[ $depth -eq 1 ] && echo "10 bit mode"
	[ $depth -eq 2 ] && echo "8 bit mode"
}

4.2.1 statically linked busybox

http://vserver.13thfloor.at/Stuff/AXIOM/FAKE/

builtin fake devmem

all you need to get it to work is the following: 

dd if=/dev/zero of=/tmp/mem bs=1k seek=4M count=1

this will create a sparse 4GB file /tmp/mem, which will be used by the fake devmem values written can be read back, non existing values return 0

/bin/sh and /sbin/devmem both link to busybox on the axiom alpha filesystem so both can be tested with this executeable

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