USB 3.0 Plugin Module Gearwork

From apertus wiki
Revision as of 15:14, 22 August 2019 by Apurvan (talk | contribs) (Created page with " PAGE UNDER CONSTRUCTION == Project Summary == The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gb...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search 
PAGE UNDER CONSTRUCTION

1 Project Summary

The AXIOM Beta currently features PCIe x1 connectors on the main board which are capable of transferring data at a rate of 6Gbit/s or more. Several high speed plugin modules like HDMI, DP or SDI can be plugged into these thereby providing additional functionalities.Currently, the AXIOM Beta lacks a USB 3.0 interface for direct transmission of RAW video data to a connected PC for recording/streaming purposes. This project is about implementing a USB 3.0 gearwork using the LVDS connection exposed by the PCIe connectors for streaming 4K 12-bit video at 25 FPS. There is no aftermarket solutions for high speed LVDS to USB 3.0 conversion. Only 16/24/32-bit parallel data to USB 3.0 bridges are available. Hence, a USB 3.0 plugin module has been designed by apertus° featuring a MachXO2 Lattice FPGA and FT601Q/FT602 FTDI IC for this purpose.

Google Summer of Code 2019 project.

Mentored by: Bertl.

'Implemented by: Apurva Nandan

2 Important URLs

- Code [1]

- Proposal [2]

- Report [3]

- Project Page at GSoC'19 [4]

- Lab Task [5]

3 References

- USB 3.0 Plugin Module Wiki [6]

- Lattice MachXO2 FPGA [7]

- Implementing High-Speed Interfaces with MachXO2 Devices - TN1203 [8]

- FTDI FT601Q chip [9]

Retrieved from "https://wiki.apertus.org/index.php?title=USB_3.0_Plugin_Module_Gearwork&oldid=8731"