PCB Sign-off Checklist

1 SCHEMATIC

• General
  • CAD ERC 100% clean (or each exception individually inspected and signed off as invalid)
  • Verify pin numbers against datasheet (if not board proven already)
  • Power/voltage/tolerance ratings specified if important
  • Verify all high-power passives and discrete semiconductors are rated for expected load voltage/current/power
  • Ceramic capacitors appropriately de-rated for C/V curve
  • Check total input capacitance and add inrush limiter if necessary
  • Polarized components specified for electrolytic caps etc\

• Power
  • All power inputs fed by correct voltage
  • Verify estimated power usage per rail against PSU ratings
  • Analog rails filtered appropriately
  • Decoupling present for all ICs
  • Bulk decoupling present at PSU
  • Shunt resistors on regulators after, not before, HF output caps
  • Decoupling meets or exceeds vendor recommendations (if specified)
  • Fusing and/or reverse voltage protection at input
  • Under/overvoltage protection configured correctly
  • Remote sense used on low voltage / high current rails
  • Verify linear regs are stable with chosen output cap ESR
  • Power gating - ensure debug interfaces are always active even in sleep
  • Verify dual-supply ICs connect thermal pads to 0V or negative supply rail as required by datasheet

• Digital Signals
  • Inputs at correct voltage levels
  • Pullups on all open-drain outputs / pulldowns on all PECL outputs
  • Termination on all high speed signals
  • AC coupling caps on transceivers
  • TX/RX paired correctly for UART, SPI, GTP, etc
  • Differential pair polarity correct
  • Verify active high/low enable signal polarity

• Analog Signals
  • RC time constant for attenuator / ADC input sane given Fsample
  • Verify frequency response of RF components for critical parameters. Don’t assume a “1 - 100 MHz” amplifier with “20 dB” gain is actually 20 dB across the whole 1-100 range.

• Boot / initialization
  • Pullups/downs on all signals that need defined state at boot
  • Strap pins connected correctly
  • JTAG/ICSP connector provided for all programmable devices
  • Config flash provided for all FPGAs
  • Power sequencing rules met
  • Reference resistors correct value and reference rail

• Debugging / reworkability
  • Use resistors vs direct connections for strap pins when possible
  • Several ground test clips
  • Dedicated ground for analog test points
  • Test points on all power rails
  • Test points on signals which may need probing

• Thermal
  • Power estimates for all large/high power ICs
  • Thermal calculations for all large ICs
  • Specify heatsinks if necessary

• Clocking
  • All oscillators meet required jitter / freq tolerance
  • Load caps on discrete crystals
  • Crystals only used if IC has a crystal driver
  • External interface protection
  • Power outputs (USB etc) current limited
  • ESD protection on exposed data lines

2 LAYOUT

• General
  • Decoupling caps as close to power pins as practical
  • No long wires from caps to vias (prefer ViP if available)
  • Layout DRC 100% clean
  • DFM / yield enhancement
  • All design rules are within manufacturer’s capability
  • Minimize use of min-sized vias and tracks where possible
  • Controlled impedance specified in fab notes if required
  • Stackup verified with manufacturer
  • Stackup specified in fab notes
  • Board finish specified in fab notes
  • If panelizing, add panel location indicators for identifying location-specific reflow issues

• Footprints
  • Components are available in the selected package
  • Schematic symbol pin numbering is valid for selected package
  • Verify pin numbering is from top vs bottom of PCB
  • PCB printed 1:1 on paper and checked against physical parts if possible
  • 3D models obtained if possible and checked against footprints
  • All pads have soldermask apertures
  • Exposed pads connected / floating according to datasheet recommendation

• Differential pairs
  • Routed differentially
  • Skew matched
  • Correct clearance to non-coupled nets

• High speed signals
  • Sufficient clearance to potential aggressors
  • Length matched if necessary
  • Avoid crossing reference plane splits/slots
  • Capacitors/vias near reference plane changes
  • Verify fab can do copper right to edge for edge launch SMA
  • Verify pad width on connectors does not cause impedance issues
  • Add plane cutouts under SMA/SFP connector, coupling cap, etc pads if needed for impedance

• Power
  • Minimal slots in power/ground planes from via antipads
  • Sufficient width for planes/traces to carry required current
  • Sensitive analog
  • Guard ring / EMI cage if necessary
  • Physically separated from large SMPS etc

• Mechanical
  • LEDS, buttons, and other UI elements on correct side of board
  • Keep-outs around PCB perimeter / mouse bites respected
  • Stress-sensitive components (MLCCs etc) not near V-score or mouse bite locations, or oriented to reduce stresses
  • Clearance around large ICs for heatsink/fan mounting if required
  • Clearance around pluggable connectors for mating half
  • Clearance around mounting holes for screws
  • Clearance under shielded connectors, magnetics, etc
  • Keep-outs for card guides etc respected
  • Overall board dimensions and mounting hole positions/sizes match enclosure/rack spec if applicable
  • Fiducials present and clearance respected (on both sides of board if required)
  • Panelisation specified if required
  • Verify mounting hole electrical connection / isolation
  • Components not physically intersecting with each other
  • Clearance around solder-down test points for probe tip
  • Consider microphone effect on MLCCs on sensitive analog rails near strong sound sources

• Thermal
  • Thermal reliefs used for plane connections if not used for heatsinking
  • Solid connections used to planes if plane is used as heat sink
  • Ensure balanced heatsinking on SMT chip components to prevent tombstoning

• Solder paste
  • No uncapped vias in pads (except for low power QFNs where some voiding is acceptable)
  • QFN pad paste prints segmented
  • Small pads 100% size, large pads reduced to avoid excessive paste

• Solder mask
  • SMD vs NSMD pads confirmed
  • Clearance around pads

• Silkscreen
  • Text size within fab limits
  • Text not overlapping drills or component pads
  • Text removed entirely in, or moved outside of, high density areas
  • Traceability markings (rev, date, name, etc)
  • Silkscreen box provided for writing/sticking serial number
  • Text mirrored properly on bottom layer

• Flex specific
  • Components oriented to reduce bending forces when possible
  • Teardrops on pads/vias

• CAM production
  • Rerun KiCAD DRC right before exporting CAM files to ensure proper zone fills
  • Export gerber and drill files at the same time even if one didn’t change
  • Visually verify final CAM files to ensure no obvious misalignments