The pinout is as follows:

Pcie conn.png
Plugin layout.png
Pin Name Function Pin Name Function
A1 GND B1 I²C SDA
A2 LVDS0 + B2 I²C SCL
A3 LVDS0 - B3 VCC I²C (typically 3v3)
A4 GND B4 IO 0 (typically 3v3)
A5 LVDS1 + B5 IO 1 (typically 3v3)
A6 LVDS1 - B6 IO 2 (typically 3v3)
A7 GND B7 IO 3 (typically 3v3)
A8 LVDS2 + B8 IO 4 (typically 3v3)
A9 LVDS2 - B9 IO 5 (typically 3v3)
A10 GND B10 IO 6 (typically 3v3)
A11 Power Good; NC B11 IO 7 (typically 3v3)
A12 GND B12 5V
A13 LVDS3 + B13 VCC (typically 3v3)
A14 LVDS3 - B14 VCCIO LVDS (typically 2v4)
A15 GND B15 GND
A16 LVDS4 + B16 LVDS5 +
A17 LVDS4 - B17 LVDS5 -
A18 GND B18 GND