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sacrificing valuable Zynq GPIOs.
sacrificing valuable Zynq GPIOs.
<gallery mode="packed" heights="180">
<gallery mode="packed" heights="150">
Image:Top.png| PCB Top.
Image:Top.png| PCB Top.
Image:Bottom.png| PCB Bottom.
Image:Bottom.png| PCB Bottom.

Revision as of 15:59, 16 January 2018

PCB Top with components
PCB Bottom with components.

1 About

The Beta Mainboard deals with interfacing the plugin modules and shields and therefore acts as a kind of data crossroad.

It features two Beta CSO slots - one on each PCB side - directly behind the image sensor center. This is intended for IMU sensors or future extensions.

The purpose of the two Lattice FPGAs (the so called routing fabrics) is to handle all the low speed GPIO stuff required for plugin modules, shields and CSO without sacrificing valuable Zynq GPIOs.

1.1 Revisions


AXIOM Beta Main Board V0.36 R1.2


AXIOM Beta Main Board V0.35

AXIOM Beta Main Board V0.33

AXIOM Beta Main Board V0.29

AXIOM Beta Board 100 v0.16

axiom beta board 100 v0.15 test