Difference between revisions of "FPGA based Bidirectional Packet Protocol"
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== Important links == | == Important links == | ||
- '''Project Proposal'''[https://github.com/Apoorva-ar/GSOC_2020/blob/master/proposal%20(1).pdf] | - '''Project Proposal'''[https://github.com/Apoorva-ar/GSOC_2020/blob/master/proposal%20(1).pdf] | ||
- '''Phase I report'''[https://github.com/Apoorva-ar/GSOC_2020/blob/master/GSOC_Apoorva_phase1_Report.pdf] | - '''Phase I report'''[https://github.com/Apoorva-ar/GSOC_2020/blob/master/GSOC_Apoorva_phase1_Report.pdf] | ||
- '''Code base'''[https://github.com/Apoorva-ar/GSOC_2020] | - '''Code base'''[https://github.com/Apoorva-ar/GSOC_2020] | ||
Latest revision as of 05:59, 21 July 2020
1 Project Summary
Under GSOC 2020 framework I am working on FPGA based bidirectional packet protocol design. The main aim of the project is to design a packet based bidirectional protocol over single LVDS link that can fully utilize the available band width based on priority based task scheduling. This will enable ZYNQ system to directly control peripherals of interface extender MACHXO2 over single LVDS link.
Google Summer of code 2020 Project
Mentors : Herbert Poetzl, Rahul Vyas
Implemented by: Apoorva Arora
2 Important links
- Project Proposal[1]
- Phase I report[2]
- Code base[3]