AXIOM Beta support for the AXIOM nMigen gateware

From apertus wiki
Revision as of 14:31, 27 August 2021 by Anuejn (talk | contribs) (Undo revision 10035 by Anuejn (talk))
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

1 Project Summary

nMigen is an HDL toolkit implemented in the Python programming language. By using nMigen instead of traditional HDLs like Verilog or VHDL, gateware can be developed in less time, with less bugs, and with extremely powerful abstractions that enable code clarity and conciseness. apertus° has already developed a prototype nMigen gateware for the AXIOM Micro camera, but wishes to extend it to support the sensor, FPGA, and HDMI interface of the AXIOM Beta. This work will develop in nMigen and demonstrate on real hardware an end-to-end imaging prototype for the AXIOM Beta: sensor control over SPI, sensor readout PHY from LVDS, pixel remapper based on existing implementation, 4K to Full HD downscaling debayerization, and final image output to HDMI.

Google Summer of Code 2021 project.

Mentored by: Herbert Poetzl (@Bertl) and Robin Heinemann (@vup)

Student: Thomas Watson (tpw_rules)

2 Important URLs

- Lab Task

- Project Page

- Source Code (see final report for details)

- Project Proposal

- Final Project Report