00-MB-001- AXIOM Beta Main Board V0.36R1.2 Bottom Populated 02 Show sm b.jpg

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The Beta Main Board is the camera's equivalent of a PC's motherboard. It hosts two external medium-speed shield connectors and two high-speed plugin module slot connectors - These act as a central switch for defining where the data that's captured by the sensor and other interfaces gets routed to inside the hardware. In this regard, all specifics can be dynamically reconfigured in software.

ABCS-MB-02a- AXIOM Beta Main Board V0.36R1.2 Top Populated sm 02.jpg

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In the centre of the Main Board, and on both sides of the PCB, a 'solder-on' area for Beta CSOs has been incorporated. CSOs host sensor chips capable of, for example, sensing the camera's orientation and acceleration (the same chips used to stabilise quad-copters and track head movements in VR headsets). Being situated directly behind the image sensor's centre means that these sensors are ideally positioned to supply data surrounding image stabilisation or metadata about the camera’s orientation and movement during a shot. Two Lattice FPGAs (the so called routing fabrics) handle all the low speed GPIO communications that are required for plugin modules, shields and CSOs without sacrificing valuable Zynq GPIOs.

ABCS-MB-02b- AXIOM Beta Main Board V0.36R1.2 Bottom Populated sm02.jpg

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The Main Board is positioned between the Interface Board and the Power Board in the camera's PCB stack (See Camera Structure).

The East shield has 4 Zynq LVDS pairs, the West shield 4 Lattice LVDS pairs (both East and West shields both have 10 North and 10 South GPIOs). LVDS paired directly from the Zynq can then be considered high speed, i.e. 1Gbit/s guaranteed and up to 1.5Gbit/s under good conditions. LVDS paired from one of the Lattice FPGAs means guaranteed up to 450Mbit, i.e. under good conditions probably around 600Mbit/s. Single ended GPIOs, regardless from where they originate, are below 300MHz at best.

Plugin Slots on the AXIOM Beta Main Board have 6 Zynq LVDS pairs and 8 GPIOs each, as well as one I2C bus for identification.

The CSO area has 2 x 4 GPIOs which can also be used as I2C or SPI buses.

1 Current Revision

AXIOM Beta Main Board V0.36 R1.2

2 Revision Archive

AXIOM Beta Main Board V0.35

AXIOM Beta Main Board V0.33

AXIOM Beta Main Board V0.29

AXIOM Beta Board 100 v0.16

axiom beta board 100 v0.15 test