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</gallery>
 
</gallery>
  
Credit: https://twitter.com/GregDavill
+
 
  
  
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[[File:Layers-pinout.jpg | 1150px]]
 
[[File:Layers-pinout.jpg | 1150px]]
  
https://docs.google.com/spreadsheets/d/17SmOY7Npzz2Hj1kz4DWKzrBAl0PYMWU085NeT3AY0D4/edit#gid=0
+
* https://docs.google.com/spreadsheets/d/17SmOY7Npzz2Hj1kz4DWKzrBAl0PYMWU085NeT3AY0D4/edit#gid=0
  
  
Line 34: Line 34:
 
a dump of the SPI communication (and the decoded flash data) can be found here:
 
a dump of the SPI communication (and the decoded flash data) can be found here:
  
http://vserver.13thfloor.at/Stuff/ELGATO/boot_decode.txt
+
* http://vserver.13thfloor.at/Stuff/ELGATO/boot_decode.txt
 +
* http://vserver.13thfloor.at/Stuff/ELGATO/boot.vcd.xz
 +
 
  
http://vserver.13thfloor.at/Stuff/ELGATO/boot.vcd.xz
+
==Further files/links==
  
 +
* http://vserver.13thfloor.at/Stuff/ELGATO/
 +
* https://github.com/ktemkin/camlink-re
  
Further files/links:
 
  
http://vserver.13thfloor.at/Stuff/ELGATO/
+
==Credits==
  
https://github.com/ktemkin/camlink-re
+
* https://twitter.com/GregDavill

Revision as of 22:38, 17 December 2019

1 PCB

It is reported to be an 8 layer PCB. Probably atleast a 2-3+ HDI.



Pinout Mapping (WIP):

Layers-pinout.jpg


2 Firmware

a dump of the SPI communication (and the decoded flash data) can be found here:


3 Further files/links


4 Credits