Difference between revisions of "FPGA based Bidirectional Packet Protocol"

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== Headline text ==
== Project Summary ==
Project Summary
 
Under GSOC 2020 framework I am working on FPGA based bidirectional packet protocol design. The main aim of the project is to design a packet based bidirectional protocol over single LVDS link that can fully utilize the available band width based on priority based task scheduling.
Under GSOC 2020 framework I am working on FPGA based bidirectional packet protocol design. The main aim of the project is to design a packet based bidirectional protocol over single LVDS link that can fully utilize the available band width based on priority based task scheduling.

Revision as of 05:35, 21 July 2020

Project Summary

Under GSOC 2020 framework I am working on FPGA based bidirectional packet protocol design. The main aim of the project is to design a packet based bidirectional protocol over single LVDS link that can fully utilize the available band width based on priority based task scheduling.